In CMOS circuits, as the technology scales down to nano scale, the sub-threshold leakage current increases with the decrease in the threshold voltage. These parameters are power dissipation, delay and how much transistors have been used in the respective designs, and then concluded that which design yields best results accordingly. Then, the comparison has been carried out for both the designs with some parameters. So in this work presents the design of single bit magnitude comparator & 3 input EXOR gate using conventional CMOS logic style as well as DCVSL style. However, the minimization of ICs has affect on leakage current when compared to the total current requirement of the circuit. The minimization of feature size plays an important role in increasing the performance of integrated circuits. The basic requirement of any Integrated Circuit is high speed and low power processing of the data signals to perform the desired execution.
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